Publicaciones (142) Publicaciones de Manuel Eugenio Acacio Sanchez

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2025

  1. ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs

    GPGPU 2025 - 17th Workshop on General Purpose Processing Using GPU

  2. No Rush in Executing Atomic Instructions

    Proceedings - International Symposium on High-Performance Computer Architecture

  3. Precise characterization of coherence activity in multicores using gem5

    Journal of Supercomputing, Vol. 81, Núm. 8

  4. WoperTM: Got Nacks? Use Them!

    IEEE Computer Architecture Letters, Vol. 24, Núm. 1, pp. 157-160

2024

  1. Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  2. On the interactions between ILP and TLP with hardware transactional memory

    Microprocessors and Microsystems, Vol. 104

2023

  1. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  2. Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing

    International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

  3. STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators

    ACM Journal on Emerging Technologies in Computing Systems, Vol. 19, Núm. 4

  4. Speculative inter-thread store-to-load forwarding in SMT architectures

    Journal of Parallel and Distributed Computing, Vol. 173, pp. 94-106

2022

  1. Analysing software prefetching opportunities in hardware transactional memory

    Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944

  2. Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory

    Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

  3. DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13

  4. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators

    Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium, IPDPS 2022

2021

  1. A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators

    Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021

  2. ITSLF: Inter-thread store-to-load forwarding in simultaneous multithreading

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  3. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    IEEE Computer Architecture Letters, Vol. 20, Núm. 2, pp. 122-125

  4. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    Proceedings - 2021 IEEE International Symposium on Workload Characterization, IISWC 2021

2020

  1. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 31, Núm. 6, pp. 1301-1315