Publicacions (124) Publicacions de Manuel Eugenio Acacio Sanchez

2024

  1. On the interactions between ILP and TLP with hardware transactional memory

    Microprocessors and Microsystems, Vol. 104

2023

  1. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  2. Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing

    International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

  3. STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators

    ACM Journal on Emerging Technologies in Computing Systems, Vol. 19, Núm. 4

  4. Speculative inter-thread store-to-load forwarding in SMT architectures

    Journal of Parallel and Distributed Computing, Vol. 173, pp. 94-106

2022

  1. Analysing software prefetching opportunities in hardware transactional memory

    Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944

  2. Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory

    Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

  3. DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13

  4. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators

    Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium, IPDPS 2022

2021

  1. A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators

    Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021

  2. ITSLF: Inter-thread store-to-load forwarding in simultaneous multithreading

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  3. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    Proceedings - 2021 IEEE International Symposium on Workload Characterization, IISWC 2021

  4. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    IEEE Computer Architecture Letters, Vol. 20, Núm. 2, pp. 122-125

2020

  1. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 31, Núm. 6, pp. 1301-1315

  3. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory

    Journal of Parallel and Distributed Computing, Vol. 145, pp. 111-123

2019

  1. CNN-Sim: Un Simulador de Arquitecturas para Procesamiento de Redes Neuronales Convolucionales

    Avances en Arquitectura y Tecnología de Computadores: Actas de Jornadas SARTECO, Cáceres, 18 a 20 de septiembre de 2019| (Servicio de Publicaciones), pp. 125-131

  2. Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems

    Concurrency Computation

  3. InsideNet: A tool for characterizing convolutional neural networks

    Future Generation Computer Systems, Vol. 100, pp. 298-315

  4. Proyecto Tetris: aprendizaje de la programación en ensamblador por piezas

    Actas de las Jornadas sobre la Enseñanza Universitaria de la Informática (JENUI), Núm. 4