Arquitectura de Computadores y Sistemas paralelos
Publications (302) Publications auxquelles un chercheur a participé
2024
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AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators
CGO 2024 - Proceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization
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Alternate Path μ-op Cache Prefetching
Proceedings - International Symposium on Computer Architecture
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Code Detection for Hardware Acceleration Using Large Language Models
IEEE Access, Vol. 12, pp. 35271-35281
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Effective Context-Sensitive Memory Dependence Prediction
Proceedings - International Symposium on High-Performance Computer Architecture
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Expanding the deep-learning model to diagnosis LVNC: limitations and trade-offs
Computer Methods in Biomechanics and Biomedical Engineering: Imaging and Visualization, Vol. 12, Núm. 1
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NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator
Proceedings - International Symposium on Computer Architecture
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On the interactions between ILP and TLP with hardware transactional memory
Microprocessors and Microsystems, Vol. 104
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POAS: a framework for exploiting accelerator level parallelism in heterogeneous environments
Journal of Supercomputing, Vol. 80, Núm. 10, pp. 14666-14693
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Plinio el Viejo. Historia Natural. Escritos sobre artes. David García López.
Imafronte, Núm. 31, pp. 254-255
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Scalability Limitations of Processing-in-Memory using Real System Evaluations
Performance Evaluation Review, Vol. 52, Núm. 1, pp. 63-64
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Scalability Limitations of Processing-in-Memory using Real System Evaluations
SIGMETRICS/PERFORMANCE 2024 - Abstracts of the 2024 ACM SIGMETRICS/IFIP PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems
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Scalability limitations of processing-in-memory using real system evaluations
Proceedings of the ACM on Measurement and Analysis of Computing Systems, Vol. 8, Núm. 1
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Uso de la IA para proporcionar retroalimentación al docente a través del análisis de las grabaciones de clases
Actas de las Jornadas sobre la Enseñanza Universitaria de la Informática (JENUI), Núm. 9, pp. 241-249
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Wrong-Path-Aware Entangling Instruction Prefetcher
IEEE Transactions on Computers, Vol. 73, Núm. 2, pp. 548-559
2023
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Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
IEEE Micro, Vol. 43, Núm. 5, pp. 55-63
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Architectural Support for Optimizing Huge Page Selection Within the OS
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023
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Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
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CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
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Fine-grain data classification to filter token coherence traffic
Journal of Parallel and Distributed Computing, Vol. 171, pp. 40-53
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Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS