Jose Luis
Abellan Miguel
Investigador "Ramon y Cajal"
Universidad Católica San Antonio
Murcia, EspañaPublicaciones en colaboración con investigadores/as de Universidad Católica San Antonio (39)
2024
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Scalability Limitations of Processing-in-Memory using Real System Evaluations
Performance Evaluation Review, Vol. 52, Núm. 1, pp. 63-64
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Scalability Limitations of Processing-in-Memory using Real System Evaluations
SIGMETRICS/PERFORMANCE 2024 - Abstracts of the 2024 ACM SIGMETRICS/IFIP PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems
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Scalability limitations of processing-in-memory using real system evaluations
Proceedings of the ACM on Measurement and Analysis of Computing Systems, Vol. 8, Núm. 1
2023
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Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
IEEE Micro, Vol. 43, Núm. 5, pp. 55-63
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GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023
2022
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Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs
Proceedings - 2022 IEEE International Symposium on Secure and Private Execution Environment Design, SEED 2022
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NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
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Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy
ACM Transactions on Architecture and Code Optimization, Vol. 20, Núm. 1
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The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators
Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium, IPDPS 2022
2021
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A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators
Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021
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GNNMark: A Benchmark Suite to Characterize Graph Neural Network Training on GPUS
Proceedings - 2021 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021
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METADOCK 2: a high-throughput parallel metaheuristic scheme for molecular docking
Bioinformatics, Vol. 37, Núm. 11, pp. 1515-1520
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STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
IEEE Computer Architecture Letters, Vol. 20, Núm. 2, pp. 122-125
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STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
Proceedings - 2021 IEEE International Symposium on Workload Characterization, IISWC 2021
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Spartan: A Sparsity-Adaptive Framework to Accelerate Deep Neural Network Training on GPUs
IEEE Transactions on Parallel and Distributed Systems, Vol. 32, Núm. 10, pp. 2448-2463
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Special issue on networks-on-chip again on the rise: From emerging applications to emerging technologies
Micromachines
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TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems
Proceedings -Design, Automation and Test in Europe, DATE
2020
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CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Design space exploration of accelerators and end-to-end DNN evaluation with TFLITE-SOC
Proceedings - Symposium on Computer Architecture and High Performance Computing