Alberto
Ros Bardisa
Catedraticos de Universidad
Publicaciones (118) Publicaciones de Alberto Ros Bardisa Ver datos de investigación referenciados.
2024
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Alternate Path μ-op Cache Prefetching
Proceedings - International Symposium on Computer Architecture
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Effective Context-Sensitive Memory Dependence Prediction
Proceedings - International Symposium on High-Performance Computer Architecture
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On the interactions between ILP and TLP with hardware transactional memory
Microprocessors and Microsystems, Vol. 104
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Wrong-Path-Aware Entangling Instruction Prefetcher
IEEE Transactions on Computers, Vol. 73, Núm. 2, pp. 548-559
2023
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CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
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Fine-grain data classification to filter token coherence traffic
Journal of Parallel and Distributed Computing, Vol. 171, pp. 40-53
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MBPlib: Modular Branch Prediction Library
Proceedings - 2023 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023
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Rebasing Microarchitectural Research with Industry Traces
Proceedings - 2023 IEEE International Symposium on Workload Characterization, IISWC 2023
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Speculative inter-thread store-to-load forwarding in SMT architectures
Journal of Parallel and Distributed Computing, Vol. 173, pp. 94-106
2022
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Analysing software prefetching opportunities in hardware transactional memory
Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944
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Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory
Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
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Berti: an Accurate Local-Delta Data Prefetcher
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
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Compiler-Assisted Compaction/Restoration of SIMD Instructions
IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 4, pp. 779-791
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Composite Instruction Prefetching
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
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DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory
IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13
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Exploring Instruction Fusion Opportunities in General Purpose Processors
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
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Free Atomics: Hardware Atomic Operations without Fences
Proceedings - International Symposium on Computer Architecture
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Splash-4: A Modern Benchmark Suite with Lock-Free Constructs
Proceedings - 2022 IEEE International Symposium on Workload Characterization, IISWC 2022
2021
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A cost-effective entangling prefetcher for instructions
Proceedings - International Symposium on Computer Architecture
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Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation
Proceedings - 2021 International Symposium on Secure and Private Execution Environment Design, SEED 2021