Publikationen, an denen er mitarbeitet Jose Ruben Titos Gil (26)

2024

  1. On the interactions between ILP and TLP with hardware transactional memory

    Microprocessors and Microsystems, Vol. 104

2022

  1. Analysing software prefetching opportunities in hardware transactional memory

    Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944

  2. Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory

    Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

  3. DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13

2020

  1. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 31, Núm. 6, pp. 1301-1315

  2. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory

    Journal of Parallel and Distributed Computing, Vol. 145, pp. 111-123

2019

  1. Proyecto Tetris: aprendizaje de la programación en ensamblador por piezas

    Actas de las Jornadas sobre la Enseñanza Universitaria de la Informática (JENUI), Núm. 4

  2. Way Combination for an Adaptive and Scalable Coherence Directory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 30, Núm. 11, pp. 2608-2623

2017

  1. Way-combining directory: An adaptive and scalable low-cost coherence directory

    Proceedings of the International Conference on Supercomputing

2015

  1. Hardware approaches to transactional memory in chip multiprocessors

    Handbook on Data Centers (Springer New York), pp. 805-835

2014

  1. Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

    Journal of Supercomputing, Vol. 68, Núm. 2, pp. 914-934

  2. ZEBRA: Data-centric contention management in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 25, Núm. 5, pp. 1359-1369

2013

  1. Eager beats lazy: Improving store management in eager hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 11, pp. 2192-2201

  2. Efficient eager management of conflicts for scalable hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 1, pp. 59-71

  3. On the design of energy-efficient hardware transactional memory systems

    Concurrency and Computation: Practice and Experience

2012

  1. Dynamic Serialization: Improving energy consumption in eager-eager hardware transactional memory systems

    Proceedings - 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012

  2. Hardware transactional memory with software-defined conflicts

    Transactions on Architecture and Code Optimization, Vol. 8, Núm. 4

  3. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory

    Proceedings - International Symposium on High-Performance Computer Architecture

2011

  1. Eager meets lazy: The impact of write-buffering on hardware transactional memory

    Proceedings of the International Conference on Parallel Processing

  2. The impact of non-coherent buffers on lazy hardware transactional memory systems

    IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum