Publikationen, an denen er mitarbeitet Alberto Ros Bardisa (39)

2024

  1. On the interactions between ILP and TLP with hardware transactional memory

    Microprocessors and Microsystems, Vol. 104

2023

  1. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  2. Speculative inter-thread store-to-load forwarding in SMT architectures

    Journal of Parallel and Distributed Computing, Vol. 173, pp. 94-106

2022

  1. Analysing software prefetching opportunities in hardware transactional memory

    Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944

  2. Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory

    Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

  3. DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13

2021

  1. ITSLF: Inter-thread store-to-load forwarding in simultaneous multithreading

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

2020

  1. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 31, Núm. 6, pp. 1301-1315

  2. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory

    Journal of Parallel and Distributed Computing, Vol. 145, pp. 111-123

2019

  1. Proyecto Tetris: aprendizaje de la programación en ensamblador por piezas

    Actas de las Jornadas sobre la Enseñanza Universitaria de la Informática (JENUI), Núm. 4

  2. Way Combination for an Adaptive and Scalable Coherence Directory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 30, Núm. 11, pp. 2608-2623

2018

  1. Photonic-based express coherence notifications for many-core CMPs

    Journal of Parallel and Distributed Computing, Vol. 113, pp. 179-194

2017

  1. A dedicated private-shared cache design for scalable multiprocessors

    Concurrency and Computation: Practice and Experience

  2. To be silent or not: on the impact of evictions of clean data in cache-coherent multicores

    Journal of Supercomputing, Vol. 73, Núm. 10, pp. 4428-4443

  3. Way-combining directory: An adaptive and scalable low-cost coherence directory

    Proceedings of the International Conference on Supercomputing

2016

  1. Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study

    Journal of Supercomputing, Vol. 72, Núm. 2, pp. 612-638

  2. Optimization of a linked cache coherence protocol for scalable manycore coherence

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2015

  1. Adaptive selection of cache indexing bits for removing conflict misses

    IEEE Transactions on Computers, Vol. 64, Núm. 6, pp. 1534-1547

  2. DASC-DIR: a low-overhead coherence directory for many-core processors

    Journal of Supercomputing, Vol. 71, Núm. 3, pp. 781-807

  3. Early experiences with separate caches for private and shared data

    Proceedings - 11th IEEE International Conference on eScience, eScience 2015