Publications by the researcher in collaboration with Manuel Eugenio Acacio Sanchez (24)

2015

  1. Adaptive selection of cache indexing bits for removing conflict misses

    IEEE Transactions on Computers, Vol. 64, Núm. 6, pp. 1534-1547

2014

  1. ZEBRA: Data-centric contention management in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 25, Núm. 5, pp. 1359-1369

2013

  1. Eager beats lazy: Improving store management in eager hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 11, pp. 2192-2201

  2. Efficient eager management of conflicts for scalable hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 1, pp. 59-71

2012

  1. ASCIB: Adaptive selection of cache indexing bits for removing conflict misses

    Proceedings of the International Symposium on Low Power Electronics and Design

  2. Extending magny-cours cache coherence

    IEEE Transactions on Computers, Vol. 61, Núm. 5, pp. 593-606

  3. Hardware transactional memory with software-defined conflicts

    Transactions on Architecture and Code Optimization, Vol. 8, Núm. 4

  4. Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE

    Journal of Supercomputing, Vol. 62, Núm. 2, pp. 787-803

  5. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory

    Proceedings - International Symposium on High-Performance Computer Architecture

2011

  1. Eager meets lazy: The impact of write-buffering on hardware transactional memory

    Proceedings of the International Conference on Parallel Processing

  2. The impact of non-coherent buffers on lazy hardware transactional memory systems

    IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum

  3. ZEBRA: A data-centric, hybrid-policy hardware transactional memory design

    Proceedings of the International Conference on Supercomputing

  4. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2010

  1. A direct coherence protocol for many-core chip multiprocessors

    IEEE Transactions on Parallel and Distributed Systems, Vol. 21, Núm. 12, pp. 1779-1792

  2. EMC2: Extending magny-cours coherence for large-scale servers

    17th International Conference on High Performance Computing, HiPC 2010

2008

  1. Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors

    Journal of Parallel and Distributed Computing, Vol. 68, Núm. 11, pp. 1413-1424

2006

  1. Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures

    Journal of Computer Science and Technology, Vol. 6, Núm. 1, pp. 1-7

2005

  1. Diseño y evaluación de una arquitectura de directorio ligero para multiprocesadores de memoria compartida escalables

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  2. Estudio y evaluación del encaminamiento multidestino en arquitecturas cc-NUMA con directorios comprimidos

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]

  3. Performance evaluation of a bus-based 16-core chip-multiprocessor

    Actas de las XVI Jornadas de Paralelismo. [JP'2005]