Toward Energy-Efficient High-Performance Organizations of the Memory Hierarchy in Chip-Multiprocessors Architectures

  1. Villa, Francisco J.
  2. Acacio Sánchez, Manuel
  3. García Carrasco, José Manuel
Revista:
Journal of Computer Science and Technology

ISSN: 1666-6038

Año de publicación: 2006

Título del ejemplar: Seventeenth Issue

Volumen: 6

Número: 1

Páginas: 1-7

Tipo: Artículo

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Otras publicaciones en: Journal of Computer Science and Technology

Resumen

Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers. CMPs require innovative designs of on-chip memory hierarchies, especially designed to address the problems that arise in this novel kind of architecture: higher memory bandwidh demand from more processing cores and the increasing latency of off-chip cache misses. Moreover, the energy consumption topic is even more pressing than in traditionalmultiprocessors, as the CMPs are commonly used in embedded systems. This paper presents a survey of some of the proposals that have recently appeared facing these topics.

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