Jose Manuel Garcia Carrasco-rekin lankidetzan egindako argitalpenak (6)

2015

  1. Soft-error mitigation by means of decoupled transactional memory threads

    Distributed Computing, Vol. 28, Núm. 2, pp. 75-90

2013

  1. Modeling the impact of permanent faults in caches

    Transactions on Architecture and Code Optimization, Vol. 10, Núm. 4

2012

  1. A fault-tolerant architecture for parallel applications in tiled-CMPs

    Journal of Supercomputing, Vol. 61, Núm. 3, pp. 997-1023

2011

  1. An analytical model for the calculation of the Expected Miss Ratio in faulty caches

    Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

2010

  1. A log-based redundant architecture for reliable parallel computation

    17th International Conference on High Performance Computing, HiPC 2010

2001

  1. Selective Branch Prediction Reversal by correlating with data values and control flow

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 228-233