Using a reconfigurable L1 data cache for efficient version management in hardware Transactional Memory

  1. Armejach, A.
  2. Seyedi, A.
  3. Titos-Gil, R.
  4. Hur, I.
  5. Cristal, A.
  6. Unsal, O.
  7. Valero, M.
Proceedings:
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

ISSN: 1089-795X

ISBN: 9780769545660

Year of publication: 2011

Pages: 361-371

Type: Conference paper

DOI: 10.1109/PACT.2011.67 GOOGLE SCHOLAR

Sustainable development goals

Data source: Scopus