New scalable cache coherence protocols for on-chip multiprocessors= Nuevos protocolos de coherencia escalables para multiprocesadores en chip

Abstract

This thesis includes an analysis of the problems associated with cache coherence in the field of chip multiprocessors (CMPs) and it introduces two new hardware-based coherence protocol proposals. Both proposals are focused on mitigating the associated cost brought by the necessity of having to use complex memory hierarchies inside the chip in order to face the memory bandwidth limitation (bandwidth-wall). On the one hand, considering as a target multicore systems with tens of processors within the chip, LOCKE is proposed. This proposal uses a broadcast-based approach, which focuses on improving the reactiveness of the on-chip memory hierarchy. On the other hand, for future large-scale CMPs which will include hundreds or thousands of processors, MOSAIC is proposed. This is a scalable hybrid coherence protocol (broadcast- and directory-based) that significantly reduces the maintenance costs of hardware coherence.