Publicacions en què col·labora amb José Duato Marín (28)

2017

  1. TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs

    IEEE Transactions on Parallel and Distributed Systems, Vol. 28, Núm. 8, pp. 2401-2413

2016

  1. Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

    IEEE Transactions on Parallel and Distributed Systems, Vol. 27, Núm. 3, pp. 748-761

  2. TokenTLB: A token-based page classification approach

    Proceedings of the International Conference on Supercomputing

2013

  1. Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks

    IEEE Transactions on Computers, Vol. 62, Núm. 3, pp. 482-495

  2. Temporal-Aware mechanism to detect private data in chip multiprocessors

    Proceedings of the International Conference on Parallel Processing

2012

  1. Cache miss characterization in hierarchical large-scale cache-coherent systems

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

  2. Extending magny-cours cache coherence

    IEEE Transactions on Computers, Vol. 61, Núm. 5, pp. 593-606

  3. PS-Dir: A Scalable Two-Level Directory Cache

    PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12)

  4. PS-Dir: A scalable two-level directory cache

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2011

  1. Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks

    ISCA 2011: PROCEEDINGS OF THE 38TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE

  2. Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks

    Proceedings - International Symposium on Computer Architecture

2010

  1. Dealing with transient faults in the interconnection network of CMPs at the cache coherence level

    IEEE Transactions on Parallel and Distributed Systems, Vol. 21, Núm. 8, pp. 1117-1131

  2. EMC2: Extending magny-cours coherence for large-scale servers

    17th International Conference on High Performance Computing, HiPC 2010

2008

  1. A fault-tolerant directory-based cache coherence protocol for CMP architectures

    Proceedings of the International Conference on Dependable Systems and Networks

  2. Extending the tokenCMP cache coherence protocol for low overhead fault tolerance in CMP architectures

    IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 8, pp. 1044-1056

  3. Fault-tolerant cache coherence protocols for CMPs: Evaluation and trade-offs

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2007

  1. A low overhead fault tolerant coherence protocol for CMP architectures

    Proceedings - International Symposium on High-Performance Computer Architecture

2005

  1. A two-level directory architecture for highly scalable cc-NUMA multiprocessors

    IEEE Transactions on Parallel and Distributed Systems, Vol. 16, Núm. 1, pp. 67-79

2004

  1. An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

    IEEE Transactions on Parallel and Distributed Systems, Vol. 15, Núm. 8, pp. 755-768

2002

  1. A. novel approach to reduce L2 miss latency in shared-memory multiprocessors

    Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002