Jose Luis
Abellan Miguel
Investigador "Ramon y Cajal"
Georgia Institute of Technology
Atlanta, Estados UnidosPublicaciones en colaboración con investigadores/as de Georgia Institute of Technology (6)
2023
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Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
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STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators
ACM Journal on Emerging Technologies in Computing Systems, Vol. 19, Núm. 4
2022
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Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators
Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium, IPDPS 2022
2021
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A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators
Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021
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STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
Proceedings - 2021 IEEE International Symposium on Workload Characterization, IISWC 2021
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STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators
IEEE Computer Architecture Letters, Vol. 20, Núm. 2, pp. 122-125