Publicaciones en colaboración con investigadores/as de Universidad Politécnica de Valencia (29)

2023

  1. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  2. Improved Converted Traces from Rebasing Microarchitectural Research with Industry Traces

    Zenodo

  3. Improved Converted Traces from Rebasing Microarchitectural Research with Industry Traces

    Zenodo

  4. Rebasing Microarchitectural Research with Industry Traces

    Proceedings - 2023 IEEE International Symposium on Workload Characterization, IISWC 2023

2019

  1. Way Combination for an Adaptive and Scalable Coherence Directory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 30, Núm. 11, pp. 2608-2623

2018

  1. TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction

    IEEE Transactions on Parallel and Distributed Systems, Vol. 29, Núm. 5, pp. 1188-1201

2017

  1. TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs

    IEEE Transactions on Parallel and Distributed Systems, Vol. 28, Núm. 8, pp. 2401-2413

  2. The Tag Filter Architecture: An energy-efficient cache and directory design

    Journal of Parallel and Distributed Computing, Vol. 100, pp. 193-202

2016

  1. A Directory Cache with Dynamic Private-Shared Partitioning

    Proceedings - 23rd IEEE International Conference on High Performance Computing, HiPC 2016

  2. A Directory Cache with Dynamic Private-Shared Partitioning

    PROCEEDINGS OF 2016 IEEE 23RD INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING (HIPC)

  3. Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

    IEEE Transactions on Parallel and Distributed Systems, Vol. 27, Núm. 3, pp. 748-761

  4. TokenTLB: A token-based page classification approach

    Proceedings of the International Conference on Supercomputing

2015

  1. PS directory: A scalable multilevel directory cache for CMPs

    Journal of Supercomputing, Vol. 71, Núm. 8, pp. 2847-2876

  2. PS-Cache: an energy-efficient cache design for chip multiprocessors

    Journal of Supercomputing, Vol. 71, Núm. 1, pp. 67-86

  3. The Tag Filter Cache: An energy-efficient approach

    Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015

2013

  1. Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks

    IEEE Transactions on Computers, Vol. 62, Núm. 3, pp. 482-495

  2. PS-Cache: An Energy-Efficient Cache Design for Chip Multiprocessors

    2013 22ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT)

  3. PS-cache: An energy-efficient cache design for chip multiprocessors

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

  4. Temporal-Aware mechanism to detect private data in chip multiprocessors

    Proceedings of the International Conference on Parallel Processing

2012

  1. Cache miss characterization in hierarchical large-scale cache-coherent systems

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012