Publicaciones en colaboración con investigadores/as de Universidad Politécnica de Valencia (19)

2023

  1. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2019

  1. Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems

    Concurrency Computation

  2. Way Combination for an Adaptive and Scalable Coherence Directory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 30, Núm. 11, pp. 2608-2623

2013

  1. Towards efficient dynamic LLC home bank mapping with NoC-level support

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2012

  1. Dynamic last-level cache allocation to reduce area and power overhead in directory coherence protocols

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Extending magny-cours cache coherence

    IEEE Transactions on Computers, Vol. 61, Núm. 5, pp. 593-606

  3. Heterogeneous NoC design for efficient broadcast-based coherence protocol support

    Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

2011

  1. Evaluation of low-overhead organizations tor the directory in future many-Core CMPs

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2010

  1. Dealing with transient faults in the interconnection network of CMPs at the cache coherence level

    IEEE Transactions on Parallel and Distributed Systems, Vol. 21, Núm. 8, pp. 1117-1131

  2. EMC2: Extending magny-cours coherence for large-scale servers

    17th International Conference on High Performance Computing, HiPC 2010

2008

  1. A fault-tolerant directory-based cache coherence protocol for CMP architectures

    Proceedings of the International Conference on Dependable Systems and Networks

  2. Extending the tokenCMP cache coherence protocol for low overhead fault tolerance in CMP architectures

    IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 8, pp. 1044-1056

  3. Fault-tolerant cache coherence protocols for CMPs: Evaluation and trade-offs

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2007

  1. A low overhead fault tolerant coherence protocol for CMP architectures

    Proceedings - International Symposium on High-Performance Computer Architecture

2005

  1. A two-level directory architecture for highly scalable cc-NUMA multiprocessors

    IEEE Transactions on Parallel and Distributed Systems, Vol. 16, Núm. 1, pp. 67-79

2004

  1. An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

    IEEE Transactions on Parallel and Distributed Systems, Vol. 15, Núm. 8, pp. 755-768

2002

  1. A. novel approach to reduce L2 miss latency in shared-memory multiprocessors

    Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

  2. Owner prediction for accelerating cache-to-cache transfer misses in a CC-NUMA architecture

    Proceedings of the International Conference on Supercomputing

  3. The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT