Manuel Eugenio
Acacio Sanchez
Catedraticos de Universidad
Universidad Politécnica de Valencia
Valencia, EspañaPublicaciones en colaboración con investigadores/as de Universidad Politécnica de Valencia (19)
2023
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CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
2019
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Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems
Concurrency Computation
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Way Combination for an Adaptive and Scalable Coherence Directory
IEEE Transactions on Parallel and Distributed Systems, Vol. 30, Núm. 11, pp. 2608-2623
2013
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Towards efficient dynamic LLC home bank mapping with NoC-level support
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2012
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Dynamic last-level cache allocation to reduce area and power overhead in directory coherence protocols
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Extending magny-cours cache coherence
IEEE Transactions on Computers, Vol. 61, Núm. 5, pp. 593-606
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Heterogeneous NoC design for efficient broadcast-based coherence protocol support
Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
2011
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Evaluation of low-overhead organizations tor the directory in future many-Core CMPs
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2010
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Dealing with transient faults in the interconnection network of CMPs at the cache coherence level
IEEE Transactions on Parallel and Distributed Systems, Vol. 21, Núm. 8, pp. 1117-1131
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EMC2: Extending magny-cours coherence for large-scale servers
17th International Conference on High Performance Computing, HiPC 2010
2008
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A fault-tolerant directory-based cache coherence protocol for CMP architectures
Proceedings of the International Conference on Dependable Systems and Networks
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Extending the tokenCMP cache coherence protocol for low overhead fault tolerance in CMP architectures
IEEE Transactions on Parallel and Distributed Systems, Vol. 19, Núm. 8, pp. 1044-1056
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Fault-tolerant cache coherence protocols for CMPs: Evaluation and trade-offs
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2007
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A low overhead fault tolerant coherence protocol for CMP architectures
Proceedings - International Symposium on High-Performance Computer Architecture
2005
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A two-level directory architecture for highly scalable cc-NUMA multiprocessors
IEEE Transactions on Parallel and Distributed Systems, Vol. 16, Núm. 1, pp. 67-79
2004
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An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration
IEEE Transactions on Parallel and Distributed Systems, Vol. 15, Núm. 8, pp. 755-768
2002
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A. novel approach to reduce L2 miss latency in shared-memory multiprocessors
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002
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Owner prediction for accelerating cache-to-cache transfer misses in a CC-NUMA architecture
Proceedings of the International Conference on Supercomputing
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The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT