Publicaciones en las que colabora con Jose Luis Abellan Miguel (25)

2023

  1. Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing

    International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

  2. STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators

    ACM Journal on Emerging Technologies in Computing Systems, Vol. 19, Núm. 4

2022

  1. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators

    Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium, IPDPS 2022

2021

  1. A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators

    Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021

  2. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    Proceedings - 2021 IEEE International Symposium on Workload Characterization, IISWC 2021

  3. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators

    IEEE Computer Architecture Letters, Vol. 20, Núm. 2, pp. 122-125

2020

  1. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2019

  1. InsideNet: A tool for characterizing convolutional neural networks

    Future Generation Computer Systems, Vol. 100, pp. 298-315

2018

  1. Photonic-based express coherence notifications for many-core CMPs

    Journal of Parallel and Distributed Computing, Vol. 113, pp. 179-194

2015

  1. Efficient hardware-supported synchronization mechanisms for manycores

    Handbook on Data Centers (Springer New York), pp. 753-803

  2. Fast and efficient commits for Lazy-Lazy hardware transactional memory

    Journal of Supercomputing, Vol. 71, Núm. 12, pp. 4305-4326

2013

  1. Deploying hardware locks to improve performance and energy efficiency of hardware transactional memory

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Design of an efficient communication infrastructure for highly contended locks in many-core CMPs

    Journal of Parallel and Distributed Computing, Vol. 73, Núm. 7, pp. 972-985

  3. ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs

    Proceedings - 2013 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013

  4. Efficient Dir0B cache coherency for many-core CMPs

    Procedia Computer Science

2012

  1. Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs

    Proceedings -Design, Automation and Test in Europe, DATE

  2. Efficient hardware barrier synchronization in many-core CMPs

    IEEE Transactions on Parallel and Distributed Systems, Vol. 23, Núm. 8, pp. 1453-1466

  3. Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE

    Journal of Supercomputing, Vol. 62, Núm. 2, pp. 787-803

2011

  1. GLocks: Efficient support for highly-contended locks in many-core CMPs

    Proceedings - 25th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2011

2010

  1. A G-line-based network for fast and efficient barrier synchronization in many-core CMPs

    Proceedings of the International Conference on Parallel Processing