Publikationen in Zusammenarbeit mit Forschern von Chalmers University of Technology (16)

2015

  1. Enhancing garbage collection synchronization using explicit bit barriers

    Proceedings of the International Conference on Parallel Processing

  2. Hardware approaches to transactional memory in chip multiprocessors

    Handbook on Data Centers (Springer New York), pp. 805-835

2014

  1. Performance and energy analysis of the restricted transactional memory implementation on haswell

    Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS

  2. Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

    Journal of Supercomputing, Vol. 68, Núm. 2, pp. 914-934

  3. ZEBRA: Data-centric contention management in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 25, Núm. 5, pp. 1359-1369

2013

  1. Eager beats lazy: Improving store management in eager hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 11, pp. 2192-2201

  2. Efficient eager management of conflicts for scalable hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 24, Núm. 1, pp. 59-71

  3. SCIN-Cache: Fast speculative versioning in multithreaded cores

    Transactions on Architecture and Code Optimization, Vol. 9, Núm. 4

  4. Techniques to Improve Performance in Requester-Wins Hardware Transactional Memory

    ACM Transactions on Architecture and Code Optimization, Vol. 10, Núm. 4, pp. 1-25

  5. Techniques to improve performance in requester-wins Hardware Transactional Memory

    Transactions on Architecture and Code Optimization, Vol. 10, Núm. 4

2012

  1. pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory

    2012 IEEE 18TH INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA)

  2. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory

    Proceedings - International Symposium on High-Performance Computer Architecture

2011

  1. Eager meets lazy: The impact of write-buffering on hardware transactional memory

    Proceedings of the International Conference on Parallel Processing

  2. The impact of non-coherent buffers on lazy hardware transactional memory systems

    IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum

  3. ZEBRA: A data-centric, hybrid-policy hardware transactional memory design

    Proceedings of the International Conference on Supercomputing

  4. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT