Metodología de diseño y síntesis sobre hardware reconfigurable de arquitecturas de procesamiento de imágenes en tiempo real

Abstract

The design of embedded computer systems is a field of research with enormous growth potential. There is an increasing need for systems capable of performing identification or recognition tasks of people, animals or objects on large images and, in the case of portable systems, with the lowest possible power consumption. However, some of these algorithms are complex and their integration on hardware is not simple, since they require, at a previous stage, a simplification that allows them to be adapted to the characteristics and limitations of the hardware resources of the electronic technology on which they are going to be implemented. On the other hand, the design of electronic computer vision systems is a process that increasingly requires the participation of engineers qualified both in the field of electronic design and artificial intelligence, and more specifically in the field of deep learning neural networks. During the last decade we have witnessed the expansion of this type of networks that have begun to replace, in some applications, classical feature extraction techniques. This fact is due in part to the flexibility they present to solve different computer vision problems in applications as diverse as robotics, medicine, autonomous transportation systems, etc. exhibiting, in many cases, an efficiency superior to that of classical identification or pattern recognition algorithms. As a result of this expansion, an ecosystem of programming languages and libraries has also been developed to facilitate and accelerate the design of this type of networks and their application on image databases of enormous size. However, the step of generating electronic designs from the designs obtained with these tools is not trivial and depends on the engineer's experience and, above all, on a long design process. This PhD Thesis deals with the study and proposal of digital hardware architectures for computer vision tasks. Specifically, the Thesis focuses on the register-level design of both modules used in feature extraction algorithms and modules used for the construction of deep learning neural networks used for object recognition and identification. In the case of feature extraction techniques, after a literature review of the most widely used algorithms, this Thesis takes as a reference the SIFT algorithm, based on the extraction and labeling of characteristic points of an image, whose first stage is common to other algorithms of this type such as SURF. The different hardware implementations of this algorithm proposed in the scientific literature tend to omit, due to its complexity, two stages that increase the number of characteristic points and the accuracy of their localization on the image. In this work, the hardware implementation of these stages has been proposed as a hypothesis to improve the performance of digital implementations of the algorithm. With respect to neural networks, this Thesis proposes the use of an automatic synthesis software tool capable of generating register-level hardware designs from the high-level descriptions of deep learning neural networks. The hypothesis proposed is that the use of this tool can generalize and make cheaper the implementation of this type of networks on embedded devices due to the reduction of the design time and the ease of implementation. The main results obtained during this PhD Thesis have been the following: i) the development and implementation at register level of two of the hardware modules used in the first stage of the SIFT algorithm. On the one hand, real-time image scaling has been developed for its application both in the first stage of the SIFT algorithm and in any other algorithm that requires this operation. On the other hand, a more complex module capable of performing sub-pixel refinement has been created to increase the accuracy of the location of the characteristic points of an image. Both modules have been designed at the register level using VHDL and synthesized on an FPGA; ii) the creation of a library of hardware modules useful for the creation of computer vision systems based on Deep learning neural networks. These modules are parameterizable, not only to be used in neural networks of different topologies, but also to provide the designer with the ability to make decisions regarding the balance between the latency of the digital system or the amount of hardware resources required for a given target technology; iii) The integration of this library of modules in a software tool capable of translating high-level descriptions of neural networks into register-level designs suitable to be synthesized on an FPGA or an ASIC. This tool has been complemented with another one dedicated to optimize the quantification of the neural network parameters as a previous step to its synthesis, an essential process to reduce the size of the network and the enormous amount of memory and processing resources required by this type of algorithms. The work carried out in this Thesis on the hardware implementation techniques of complex vision algorithms lays the foundations to deepen in the design of the so-called edge computing, in which the processing of the data captured by a sensor is performed in the sensor itself or on an attached device whose computational capacity is several orders of magnitude lower than that of a central server. In this line, the results obtained are equally applicable to the development of new vision devices implemented on embedded hardware or on portable devices that need processing algorithms adapted to their characteristic requirements of small size or low energy consumption. Finally, the contribution in the field of electronic design automation opens the way to deepening the development of CAD tools that reduce the development cycle time of a product, making it more competitive.