Dynamic Cache Blocks Mapping to Reduce Last-Level Cache Access Latency

Resumen

In tiled Chip Multiprocessors (CMPs)the banks of the built-in last level cache (LLC)are usually distributed among the tiles and logicallyshared. A static mapping of cache blocks to the LLCbanks leads to poor efficiency since a block can bemapped to a bank far away from the tiles which actuallyaccess it. Partially dynamic policies have beenproposed, which however rely on the static mappingof blocks to a set of banks (D-NUCA) or rely on theOS to dynamically load pages to statically mappedaddresses (first-touch).We propose a new dynamic approach where theLLC home bank is determined at runtime in hardware,with the memory controller in charge to performthe block mapping when fetched from mainmemory. To speed up the home bank lookup process,we use simple and lightweight NoC optimizations.When compared to alternative solutions (SNUCA,D-NUCA, first touch, private LLCs) resultswith PARSEC and SPLASH-2 applications indicateimprovement in locality of LLC blocks in the sametile (56.2% from 5.8%) and more than 33% reductionin load and store miss latencies. This leads to an averagereduction of 24% in application’s execution timecompared to static mapping.