Publications (81) Alberto Ros Bardisa publications View referenced research data.

filter_list Hardware and Architecture

2024

  1. Alternate Path μ-op Cache Prefetching

    Proceedings - International Symposium on Computer Architecture

  2. Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  3. Effective Context-Sensitive Memory Dependence Prediction

    Proceedings - International Symposium on High-Performance Computer Architecture

  4. Enhanced System-Level Coherence for Heterogeneous Unified Memory Architectures

    Proceedings - 2024 IEEE International Symposium on Workload Characterization, IISWC 2024

  5. Hardware Cache Locking for All Memory Updates

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

  6. On the interactions between ILP and TLP with hardware transactional memory

    Microprocessors and Microsystems, Vol. 104

  7. Temporarily Unauthorized Stores: Write First, Ask for Permission Later

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  8. Wrong-Path-Aware Entangling Instruction Prefetcher

    IEEE Transactions on Computers, Vol. 73, Núm. 2, pp. 548-559

2022

  1. Analysing software prefetching opportunities in hardware transactional memory

    Journal of Supercomputing, Vol. 78, Núm. 1, pp. 919-944

  2. Analysis of the Interactions between ILP and TLP with Hardware Transactional Memory

    Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

  3. Berti: an Accurate Local-Delta Data Prefetcher

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  4. Composite Instruction Prefetching

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

  5. DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

    IEEE Transactions on Parallel and Distributed Systems, Vol. 33, Núm. 1, pp. 1-13

  6. Exploring Instruction Fusion Opportunities in General Purpose Processors

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO

  7. Free Atomics: Hardware Atomic Operations without Fences

    Proceedings - International Symposium on Computer Architecture

  8. Splash-4: A Modern Benchmark Suite with Lock-Free Constructs

    Proceedings - 2022 IEEE International Symposium on Workload Characterization, IISWC 2022

2021

  1. A cost-effective entangling prefetcher for instructions

    Proceedings - International Symposium on Computer Architecture

  2. Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation

    Proceedings - 2021 International Symposium on Secure and Private Execution Environment Design, SEED 2021

  3. Splash-4: Improving Scalability with Lock-Free Constructs

    Proceedings - 2021 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021

2020

  1. Boosting store buffer efficiency with store-prefetch bursts

    Proceedings of the Annual International Symposium on Microarchitecture, MICRO